Exceptions in ARM

[Timo Sintonen]

On Saturday, 1 March 2014 at 07:53:45 UTC, Mike wrote:
> On Saturday, 1 March 2014 at 07:26:16 UTC, Timo Sintonen wrote:
>>>> I investigated this a little. It seems that the processor 
>>>> gets a fault interrupt when calling _Unwind_RaiseException 
>>>> in _d_throw. The status bits indicate an invalid instruction 
>>>> code.
>>>> When looking at the disassembly I see that the call is a blx 
>>>> instruction with address. In Cortex-m4 blx can only take a 
>>>> register argument.
>>>> Is this a bug in gdc or gcc?
>>>
>>> blx can also take a label.  Are you sure it's an address and 
>>> not
>>> a label?
>>
>> According to the instruction card
>> http://infocenter.arm.com/help/topic/com.arm.doc.qrc0006e/QRC0006_UAL16.pdf
>> blx with label is valid in thumb instruction set. But it is a 
>> 32
>> bit instruction so I think it does not exist in any thumb only
>> processors.
>>
>> Here we can see it is not valid in M4:
>> http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/BABEFHAE.html
>
> It is my understanding that Thumb is 16-bit only, but Thumb-2 is
> a mix of 16 and 32-bit instructions
> (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/CHDFEDDB.html).
>   Under the "Specifications" tab of this site
> (http://www.arm.com/products/processors/cortex-m/cortex-m4-processor.php)
> it shows the Cortex-M4 as a Thumb-2 capable core.
>
> I don't know how to tell GDC/GCC to only generate Thumb-1 as
> opposed to Thumb-2 so it's my assumption it will default the
> latest Thumb based on the specified arch or cpu argument.  In
> that case, I think it will generate Thumb-2 instructions.
> Correct me if I'm wrong.
>
> Here's the instruction card for Thumb-2
> (http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001l/QRC0001_UAL.pdf).
>   It shows the blx <label> instruction is valid for 5T and later
> architectures.  The Cortex-M4 is ARMv7EM architecture, so I 
> think
> it should be good to go.
>
> However, your second think doesn't show the blx {label} syntax,
> so I'm a little confused.
>
> Can you post the assembly code?

Here, (chapter 1.1)
http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf
"The Cortex-M4 implements a __version__ of the thumb instruction
set __based__ on thumb2."
So it is thumb2 but maybe a little modified.

There is nothing interesting in the assembly, only this wrong
call.
This form of instruction is just missing in M4 and it gives an
invalid instruction fault. So what are we arguing about?

If this is so hard for us to find, no wonder the compiler writers
have not noticed this.