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<body><span class="vcard"><a class="email" href="mailto:jens-bugzilla@gpio.dk" title="Jens Bauer <jens-bugzilla@gpio.dk>"> <span class="fn">Jens Bauer</span></a>
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<a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED WONTFIX - Add support for attribute to mark data as volatile."
href="http://bugzilla.gdcproject.org/show_bug.cgi?id=126">bug 126</a>
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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED WONTFIX - Add support for attribute to mark data as volatile."
href="http://bugzilla.gdcproject.org/show_bug.cgi?id=126#c23">Comment # 23</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED WONTFIX - Add support for attribute to mark data as volatile."
href="http://bugzilla.gdcproject.org/show_bug.cgi?id=126">bug 126</a>
from <span class="vcard"><a class="email" href="mailto:jens-bugzilla@gpio.dk" title="Jens Bauer <jens-bugzilla@gpio.dk>"> <span class="fn">Jens Bauer</span></a>
</span></b>
<pre>(In reply to Johannes Pfau from <a href="show_bug.cgi?id=126#c22">comment #22</a>)
<span class="quote">> The volatileLoad/Store intrinsics will have to suffice.</span >
Are these guaranteed to be in the specified order for volatileLoad/Store,
assuming a, b, c and d are different memory locations:
read a
write b
read c
read d
-Or would the compiler be able to mess up the order ?
I believe it's important to be able to keep the order exactly, so that you can
transfer data using several ports.
Simple (pseudo-code) example: SWD protocol
SWDIO_DIR = 0; /* data direction = input */
SWCLK = 0; /* clock pin low */
i = SWDIO; /* read data */
SWCLK = 1; /* clock pin high */
SWDIO_DIR = 1; /* data direction = output */
SWDIO = o; /* write bit 'o' */
SWCLK = 0; /* clock pin low */
cast(void)SWDIO; /* read value but throw it away. (this delay is required) */
SWCLK = 1; /* clock pin high */
... A much more advanced example would be to have multiple clock pins and
multiple ports where we read/write many bits on each port.</pre>
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