Manfred Nowak wrote: > AMD announces one further step in SIMD: > > http://developer.amd.com/articles.jsp?id=171&num=1 > > -manfred From what I can tell it's vectorized 128-bit ops, allowing, say, 4 floats to be added to another 4 floats in one op. Didn't we have that already in SSE3? Is this just AMD's version of SSE3? Anyone know what's different? --bb