new cpuid is ready for comments

[Ilya Yaroshenko via Digitalmars-d-announce]

On Tuesday, 12 July 2016 at 15:24:29 UTC, Guillaume Chatelet 
wrote:
> On Tuesday, 12 July 2016 at 13:23:46 UTC, Ilya Yaroshenko wrote:
>> On Tuesday, 12 July 2016 at 12:46:26 UTC, Guillaume Chatelet 
>> wrote:
>>> On Monday, 11 July 2016 at 16:30:44 UTC, Ilya Yaroshenko 
>>> wrote:
>>>> Hello :-)
>>>>
>>>> `cpuid` package is core.cpuid analog.
>>>> It would be used by future D BLAS implementation.
>>>
>>> Hey Ilya,
>>>
>>> Quick question: where do the data come from/how reliable do 
>>> you think they are?
>>
>> Hello Guillaume,
>>
>> The data come from CPUID x86/x86_64 instruction.
>> I have fixed bugs for AMD yesterday. Information for Intel and 
>> AMD processors should be reliable. But I am not sure about 
>> Cache and TLB information for virtual machines and other 
>> vendors. You can use cpuid.x86_any._cpuid [1] to get any 
>> information that is not presented.
>>
>> [1] 
>> http://docs.cpuid.dlang.io/latest/cpuid_x86_any.html#._cpuid
>
> Thx Ilya,
>
> I was discussing this a few colleagues. I'm quoting one of them 
> here with his permission:
>
> "It doesn't seems that a userland library like this has any 
> possibility to solve the root problem on Android/ARM. It's a 
> twofold problem:
>
> 1. On ARM, the registers containing CPU identification and 
> cache structure information, are privileged. See:
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344f/Chdebced.html
> etc... (more such registers listed in the left pane on that 
> page)
>
> Thus it is up to the operating system to expose this 
> information to userspace. That takes us to the second part of 
> the problem:
>
> 2. As far as I know, Android does not expose either CPU 
> identification or cache structure information to userspace.
>
> Please do correct me if I'm wrong and this library found a way 
> around that --- but from a cursory look at the cpuid library 
> code, it does not have an ARM implementation at the moment?"

Thank you for the information, I have not know that registers are 
privileged on ARM! By "other vendors" I mean other x86 vendors 
listed in enum VendorIndex [1]. ARM is not supported, but API 
supports complex topology. So ARM direction is to receive 
approximate information from an OS, like from /proc/cpuinfo on 
Linux. Just CPU brand name with version is significant 
information for cache size.

[1] 
http://docs.cpuid.dlang.io/latest/cpuid_x86_any.html#.VendorIndex