CT Information about target CPU and Related cross-compile

[Ilya Yaroshenko via digitalmars-d-ldc]

Hi all,

I will write std.blas and it will be heavily optimised for LDC. 
Can these features be added to LDC?

1. Basic compile time information about target CPU such as 
L1/L2/L3 cache sizes and available instructions set, e.g. SSE2, 
AVX, AVX2, AVX512.

2. Related cross-compile. For example: target is x86_64; AVX 
support can be checked at runtime using core.cpuid; so I want to 
force LDC to compile three versions of BLAS for SSE, AVX and 
AVX512, and choose better in runtime.

Links:
std.blas annonce: 
http://forum.dlang.org/thread/nilhvnqbsgqhxdshpqfl@forum.dlang.org