CT Information about target CPU and Related cross-compile
Ilya Yaroshenko via digitalmars-d-ldc
digitalmars-d-ldc at puremagic.com
Sun Dec 27 15:47:41 PST 2015
On Sunday, 27 December 2015 at 17:34:26 UTC, Johan Engelen wrote:
> On Saturday, 26 December 2015 at 20:47:39 UTC, Ilya Yaroshenko
>> Hi all,
>> I will write std.blas and it will be heavily optimised for LDC.
> jay! :-)
>> Can these features be added to LDC?
>> 1. Basic compile time information about target CPU such as
>> L1/L2/L3 cache sizes and available instructions set, e.g.
>> SSE2, AVX, AVX2, AVX512.
> Do you have a proposal for a set of function names / version
> IDs / ...? This sounds like a simple thing to add.
> I'm not sure about cache sizes: is it currently possible to
> specify the target microarchitecture on the cmdline?
I have found that core.cpuid can provide runtime information
about cache sizes, it is enough. However amount of SIMD registers
and their sizes should be known at compile time.
What do you mean with "set of function names / version IDs"?
>> 2. Related cross-compile. For example: target is x86_64; AVX
>> support can be checked at runtime using core.cpuid; so I want
>> to force LDC to compile three versions of BLAS for SSE, AVX
>> and AVX512, and choose better in runtime.
> Something like this?
Yes! Or runtime check at least.
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