Bad codegen for ARM (and maybe others) when optimizing

[Dan Olson via digitalmars-d-ldc]

"Kai Nacke" <kai at redstar.de> writes:

> Hi Dan!
>
> On Wednesday, 4 February 2015 at 16:15:47 UTC, Dan Olson wrote:
>> This looks to be the same problem.  All the fixes should be in
>> LLVM-3.6
>> which I have not tried yet (does LDC work with 3.6?).
>
> Thanks for the hint! LDC works with LLVM 3.6 out of the box.
>
> Regards,
> Kai

Thanks.  I updated to LLVM 3.6 and it does not fix the ARM problem.  I
looked at the changes for http://llvm.org/bugs/show_bug.cgi?id=20280 and
they are specific to PPC target :-(

I have been looking at IR.  The bug is connected to using the byval
attribute.  I checked out clang's IR and it does not use byval for
structs.  It passes structs as an array.  I am wondering if LDC could
use a abi-arm.cpp to generate something like clang.

For example, with these declarations:

  struct A {int value, x,y, z;}
  A fun(A a);

clang IR for ARM:
  %struct.A = type { i32, i32, i32, i32 }
  declare void @fun(%struct.A* sret, [4 x i32]) #1

where as LDC is generating:
  %badopt.A = type { i32, i32, i32, i32 }
  declare fastcc void @_D6badopt3funFS6badopt1AZS6badopt1A(%badopt.A* noalias sret, %badopt.A* byval)

The other alternative is to try to duplicate the PPC LLCM fix in my
forked LLVM repo and submit a llvm bug report.
--
Dan