C to D, HtoD fails

[Steve Horne]

On Sun, 10 Sep 2006 13:34:45 +0100, Stewart Gordon
<smjg_1998 at yahoo.com> wrote:

>> Being extremely pedantic, I think it's possible to compile for a 
>> memory model with far pointers that are bigger than 32-bit.
>
>Do such compilers/languages actually call it "far"?  Could be confusing....

Dunno. Never done it. May be completely wrong about it - just an idea
I picked up somewhere.

>Interesting facts: The ZX Spectrum (16K/48K models at least) was an
>8-bit machine with a flat 16-bit address space.

Yeah - same on most 8 bit chips. I had a Commodore myself ;-)

>  16-bit on PCs relies on
>both 16-bit (near) and 32-bit (far) memory addresses.

Pedantism two : A far pointer may have been 32 bits wide, but it only
addressed a 20 bit address space.

The 68000 was a 16 bit chip that addressed 24 bits. But then, in some
ways it was a 32 bit chip. 32 bit registers, mainly, including address
registers. When a later 68000-series chip supported a 32 bit address
bus, it didn't need any change to the registers or instruction set.

In fact, just what defines the 8/16/32/64 bittiness of a chip?
Register width? Data bus width? Address bus width? Width of a chunk of
an instruction?

In some ways, the original Pentium was a 64 bit chip. 64 bit
registers, 64 bit data bus IIRC. Could MMX instructions process 128
bits of data at a time in the earliest Pentium MMX chips? SSIMD/3DNow
instructions certainly handle 128 bits (4 floats) at a time, and have
done for some time.

These days, the data bus is already much wider than 64 bits. Nothing
to do with what an instruction can process at once, just shifting
cache pages in and out as quick as possible.

Yet in terms of the width of a chunk of an instruction, the current 64
bit desktop CPUs are still 8 bit chips. Instruction opcodes that
worked on the original 8086 and 8088 about 20 years ago still work
now, and the 8086 was criticised for not really being 16 bit when it
was released because of the 8-bit instruction coding.

So you could argue that your average P4-generation chip is 8 bit, or
128 bit, or maybe more based on the data bus.

Not to disrespect 64 bit, mind you. It's not just meaningless
marketing. Nothing like the Intel marketing claiming that dual cores
are necessary just to run a web browser and listen to music at the
same time (how many times have we been sold multitasking so far? DOS
TSRs, nonpreemptive, preemptive, separate address spaces,
multiprocessor support, and how many meanings did I miss?)

Just seems a bit daft.

>> Even 32 bit processors could have >4GB memory.
><snip>
>
>I'd be surprised to see more than 4GB on the _processor_....

LOL!

But then again, in ten years or so...

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