"The total size of a static array cannot exceed 16Mb."

[BCS]

Reply to Vladimir,

> On Wed, 03 Oct 2007 02:31:47 +0300, BCS <ao at pathlink.com> wrote:
> 
>> I think we are referring to the same thing, but counting different
>> parts of it. What I'm counting is the times that a load is done from
>> an address that is not an inline value, but comes from a register.
>> 
> OK, so in the first array example that makes one load (only the value
> we need), and in the second - two (one to get the address of the array
> data, and another to get the value).
> 

yes, assuming that you have to do some pointer work to get the array (if 
it's a static variable than you can do a "move from inline defined address")

>>> readValue proc near
>>> mov     eax, ds:bigArr[eax*4]
>> If I'm reading this correctly what is happening here is "load address
>> (bigArr + eax*4)
>> 
> No, that gets the value directly and puts it in eax. To get the
> address I would use the "lea" instruction instead of "mov" (which is
> useful if you want to read and then write to the address).
> 

Baahhh. I need to be more careful with what I actually say

that should have been "load from address"

>> unless IA32 has a special case op for that, your going to have to
>> compute
>> the address in another op and even if there is a special case, I
>> rather suspect
>> that it will be exactly as fast either way. Furthermore, if more than
>> one
>> detention is used you will have to do the computation in other ops no
>> mater
>> what.
> I posted the disassembly listing of the D code I supplied, so this
> code works (there are no missing instructions).
> 
[...]
>> It looks like you are using a (constA + Constb * reg) address mode. I
>> just look in the "Intel Architecture Software Developer's Manual" and
>> didn't find any reference to it. Am I missing something? (I didn't
>> actual look real hard)
>> 
> ConstB must be a power of 2 - and I don't think I can find a link more
> easily than you (since I don't use any online - or any other, actually
> - reference). As WB mentioned in another reply, there's also a [reg1 +
> reg2*powerOfTwo + offset] addressing mode.
> 

sweet

BTW I find these kida handy

http://www.intel.com/design/processor/manuals/253665.pdf    Volume 1: Basic 
Architecture
http://www.intel.com/design/processor/manuals/253666.pdf    Volume 2A: Instruction 
Set Reference, A-M
http://www.intel.com/design/processor/manuals/253667.pdf    Volume 2B: Instruction 
Set Reference, N-Z


foud here
http://www.intel.com/products/processor/manuals/index.htm

In the end I rather suspect that what really matters is how many times you 
read from memory, not how you got the address to read from.