Multicores and Publication Safety

[Jb]

"Walter Bright" <walter at nospammm-digitalmars.com> wrote in message 
news:g7b7h1$aeb$1 at digitalmars.com...
>>
>> > 2. Intel may change this behavior on future x86's, which means your 
>> > code
>> > will break years from now
>>
>> I dont think they could because i think a lot of code probably already 
>> relys
>> on it. And i think it's likely that the new comitment to strong memory
>> ordering, from both AMD and INTEL (both have pdfs regarding 64 bit that
>> specify it), is mainly because they realize it is needed to help progress
>> with multi core.
>
> I think that is because the current language technology is deficient. We 
> aim to fix that with D :-)

FWIW i think you're right.

But a little more help from the hardware would be nice aswell. I'd like to 
see "lock free" (non blocking) syncronization made a bit easier, somthing 
like a double CAS.