Unofficial wish list status.(Jul 2008)

[Oskar Linde]

Simen Kjaeraas wrote:
>> Walter Bright wrote:
>>> You have to be very wary of cache effects when
>>> writing data in one thread and expecting to see it in another.
>>
>> Are you saying that there is some combination of OS and/or hardware L1/L2
>> caching that would allow one thread to read a memory location 
>> (previously)
>> modified by another thread, and see 'old data'?
>>
>> Cos if you are, its a deeply serious bug that if its not already very 
>> well
>> documented by the OS writer or hardware manufacturers, then here's 
>> your chance
>> to get slashdotted (and diggited and redited etc. all concurrently) as 
>> the
>> discoveerer of a fatel processor flaw.
> 
> I don't think that's exactly what he means. If I understand things
> correctly, if one thread is going to read something, that something
> might be put in cache /before/ the other thread writes its data there.
> So yes, it is previously written, at the time the read 'should' take
> place.

Cache coherency is a very important element of any SMP design. It 
basically means that caches should be fully transparent, i.e. the 
behavior should not change by the addition or removal of caches.

So the above scenario should never occur. If thread A writes something 
prior to thread B reading it, B should never get the old value.

-- 
Oskar