D vs C++

[Andrej Mitrovic]

On 12/27/10, Andrei Alexandrescu <SeeWebsiteForEmail at erdani.org> wrote:
> I hope I placed a winning bet with D's NDS (no-default-sharing)
> concurrency model; only time will tell.
>

Excerpt from a recent article:

"Initial multicore chip architectures depended on a set of protocols
that assures that each core has the same view of the system's memory,
a technique called cache coherency.

As more cores are added to chips, this approach becomes problematic
insofar that "the protocol overhead per core grows with the number of
cores, leading to a 'coherency wall' beyond which the overhead exceeds
the value of adding cores," the paper accompanying Mattson's talk
noted.

Mattson has argued that a better approach would be to eliminate cache
coherency and instead allow cores to pass messages among one another.
"

http://www.goodgearguide.com.au/article/368762/intel_1_000-core_processor_possible/