Errors in TDPL

[Alix Pexton]

Does anyone else feel that the following is a fair clarification?

Page 396
...
	This means that communicating processors "forget" the exact order in 
which data was written: one tread writes x and then y and for a while 
another thread sees the new y but only the old x.

vvv

	This means that communicating processors "forget" the exact order in 
which data was written: one tread writes to x and then to y and for a 
while another thread sees the new value of y but only the old value of x.

...


Once I got my head around what is being claimed, I realised that it is 
correct as it appears, but it took me several reading to get there. It 
might just be because I'm a bit of a concurrency novice, but I'm sure 
I'm not the only one with a copy of tDPL ^^

A...