Word Tearing: Still a practical problem?

dsimcha dsimcha at yahoo.com
Mon Mar 21 14:10:27 PDT 2011


== Quote from bearophile (bearophileHUGS at lycos.com)'s article
> dsimcha:
> > Is writing to adjacent but
> > non-overlapping memory addresses concurrently from different threads safe on
> > all hardware we care about supporting?
> Aren't some problems caused by writing on the same cache line?
> Bye,
> bearophile

I think you're referring to false sharing.  If so, this is only a performance
problem, nit a correctness problem.  If not, please elaborate.  Also, on x86,
cache coherency circuitry make the cache much more transparent than on some
architectures.  I'm not so sure about others.


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