Something needs to happen with shared, and soon.

[Rainer Schuetze]

On 11/14/2012 3:05 AM, Alex Rønne Petersen wrote:
> On 14-11-2012 03:02, Andrei Alexandrescu wrote:
>> On 11/13/12 5:58 PM, Alex Rønne Petersen wrote:
>>> On 14-11-2012 02:52, Andrei Alexandrescu wrote:
>>>> On 11/13/12 3:48 PM, Alex Rønne Petersen wrote:
>>>>> Slices and delegates can't be loaded/stored atomically because very
>>>>> few
>>>>> architectures provide instructions to atomically load/store 16
>>>>> bytes of
>>>>> data (required on 64-bit; 32-bit would be fine since that's just 8
>>>>> bytes, but portability is king). This is also why ucent, cent, and
>>>>> real
>>>>> are not included in the list.
>>>>
>>>> When I wrote TDPL I looked at the contemporary architectures and it
>>>> seemed all were or were about to support double-word atomic ops. So the
>>>> intent is to allow shared delegates and slices.
>>>>
>>>> Are there any architectures today that don't support double-word load,
>>>> store, and CAS?
>>>>
>>>>
>>>> Andrei
>>>
>>> I do not know of a single architecture apart from x86 that supports >
>>> 8-byte load/store/CAS (and come to think of it, I'm not so sure x86
>>> actually can do 16-byte load/store, only CAS). So while a shared
>>> delegate is doable in 32-bit, it isn't really in 64-bit.
>>
>> Intel does 128-bit atomic load and store, see
>> http://www.intel.com/content/www/us/en/processors/itanium/itanium-architecture-software-developer-rev-2-3-vol-2-manual.html,
>>
>> "4.5 Memory Datum Alignment and Atomicity".
>>
>> Andrei
>>
>
> That's Itanium, though, not x86. Itanium is a fairly high-end,
> enterprise-class thing, so that's not very surprising.
>

On x86 you can use LOCK CMPXCHG16b to do the atomic read: 
http://stackoverflow.com/questions/9726566/atomic-16-byte-read-on-x64-cpus

This just excludes a small number of early AMD processors.