More radical ideas about gc and reference counting

[deadalnix via Digitalmars-d]

On Wednesday, 30 April 2014 at 23:27:49 UTC, Andrei Alexandrescu 
wrote:
> On 4/30/14, 4:14 PM, deadalnix wrote:
>> On Wednesday, 30 April 2014 at 23:05:29 UTC, Andrei 
>> Alexandrescu wrote:
>>> Sorry, I misread your code. I meant to say on x86 there's no 
>>> need to
>>> do any handshake on the single-threaded case. -- Andrei
>>
>> You don't need it on most arch. Except alpha, I don't know any 
>> that
>> would require it.
>
> So much the better. How about ARM? All I know is it's very 
> relaxed. -- Andrei

It is expected that a barrier (dmb on ARM) is inserted when 
sharing information (in std.concurency for instance). So you 
should have some initialized value in there. It can be anything 
though.

That mean that the load can get any value that was there since 
the last sharing done properly. It doesn't matter which one we 
get as they all have the same parity.

This value can't be used in the atomic branch. That is why the 
pseudo-assembly code I posted do not use the counter value in the 
atomic branch.