Testing some singleton implementations

Benjamin Thaut code at benjamin-thaut.de
Fri Jan 31 06:20:01 PST 2014


Am 31.01.2014 12:44, schrieb Andrej Mitrovic:
> On 1/31/14, Benjamin Thaut <code at benjamin-thaut.de> wrote:
>> For x86 CPUs you don't really need MemoryOrder.acq as reads are atomic
>> by default.
>
> Hmm, I guess we could use a version(X86) block to pick this. When you
> say x86, do you also imply X86_64? Where can I read about the memory
> reads being atomic by default?
>

It depends on the processor architecture. Usually if you have a "normal" 
CPU architecture it garantuees a consitent view to memory. Meaning all 
reads and writes are atomic. (But not read modify write, or even read 
write). Usually only numa architectures don't garantuee a consitent view 
of memory, resulting in reads and writes not beeing atomic. For example 
the Intel Itanium architecture does not garantuee this. But usually all 
single processor architectures garantuee a consitent view of memory. I 
did not come arcross one yet, that didn't do so. (so ARM, PPC and X86, 
X86_64 all have atomic read/writes)

Also see: http://en.wikipedia.org/wiki/Cache_coherence


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