On heap segregation, GC optimization and @nogc relaxing
ponce via Digitalmars-d
digitalmars-d at puremagic.com
Wed Nov 12 03:51:10 PST 2014
On Wednesday, 12 November 2014 at 11:19:59 UTC, Ola Fosheim
Grøstad wrote:
> STM = software based transactional memory (without hardware
> support)
I was meaning HTM instead, good catch.
> Haswell does not have buffered transactions so you wait for the
> commit, but there are presentations out where Intel has put
> buffered transactions at around 2017… (but I would expect a
> delay).
I wasn't arguing of the current performance (which is not
impressive).
My point is that transactional memory has limited applicability,
since locks already fits the bill well. And I'd argue the same
with most lockfree structures actually.
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