H1 2015 Priorities and Bare-Metal Programming

[Walter Bright via Digitalmars-d]

On 2/2/2015 1:24 PM, Johannes Pfau wrote:
> What's your argument?
> That it still generates 2 instructions in the simplest case? That's an
> X86 specific detail. On ARM and other RISC architectures there is a
> difference between loading a literal (code into the instruction) or
> loading a runtime value. On AVR gcc can even rewrite bit-sized stores
> into set-bit and loads into read-bit instructions, but it needs to
> know the addresses at compile time. If you don't believe me get an
> AVR/ARM compiler and try it.

A code generator for a specific architecture will naturally generate code that 
caters to it. volatileLoad()/Store() does not impede that, and a pragma(address) 
will not help.