Any usable SIMD implementation?
Johan Engelen via Digitalmars-d
digitalmars-d at puremagic.com
Sat Apr 23 03:40:12 PDT 2016
On Monday, 18 April 2016 at 00:27:06 UTC, Joe Duarte wrote:
>
> Someone else said talked about marking "Broadwell" and other
> generation names. As others have said, it's better to specify
> features. I wanted to chime in with a couple of additional
> examples. Intel's transactional memory accelerating
> instructions (TSX) are only available on some Broadwell parts
> because there was a bug in the original implementation (Haswell
> and early Broadwell) and it's disabled on most. But the new
> Broadwell server chips have it, and it's a big deal for some DB
> workloads. Similarly, only some Skylake chips have the Secure
> Guard instructions (SGX), which are very powerful for creating
> secure enclaves on an untrusted host.
Thanks, I've seen similar comments in LLVM code.
I have a question perhaps you can comment on?
With LLVM, it is possible to specify something like "+sse3,-sse2"
(I did not test whether this actually results in SSE3
instructions being used, but no SSE2 instructions). What should
be returned when querying whether "sse3" feature is enabled?
Should __traits(targetHasFeature, "sse3") == true mean that
implied features (such as sse and sse2) are also available?
More information about the Digitalmars-d
mailing list