Wait-free thread communication
Ola Fosheim Grøstad via Digitalmars-d
digitalmars-d at puremagic.com
Sat Jan 9 07:16:43 PST 2016
On Saturday, 9 January 2016 at 14:20:18 UTC, Andy Smith wrote:
> I'm a little worried you have no volatile writes or fences
> around your code when you 'publish' an event using head/tail
> etc. It looks like it's working but how are you ensuring no
> compiler/CPU reordering is ocurring. Does x86_64 actually allow
> you to get away with this? I know its memory model is stricter
> than others...
But not on ARM, so he should use atomic acquire-release semantics
on indices for push/pull.
I suggest porting over spsc_queue from Boost.
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