Non-x86 targets for DMD

Patrick Schluter via Digitalmars-d digitalmars-d at puremagic.com
Thu May 25 15:11:34 PDT 2017


On Thursday, 25 May 2017 at 21:15:57 UTC, Patrick Schluter wrote:
> On Thursday, 25 May 2017 at 20:47:42 UTC, solidstate1991 wrote:
>> On Monday, 22 May 2017 at 14:49:46 UTC, Stefan Koch wrote:
>>>
>>> Conditional execution is not in the later models of ARM, I 
>>> believe.
>>> Also does not really provide advantages over conditional 
>>> jumps, except in rare circumstances.
>>
>> That might be the case, maybe that's how they made space to 
>> address the 32 registers by cutting the rarely used 
>> conditional execution function.

Of course you're right, that's how they reused the 4 bits freed 
by the predicates. I should not answer posts when I'm half asleep.

>
> No, they removed it from AArch64 because it complicates things 
> on modern Out Of Order Execution high performance CPU. It was a 
> brillant idea on the original ARM design that had no caches and 
> a very small transistor budget, but doesn't bring much, or even 
> is hindering, in the times of pipelining, OOOE and branch 
> predictions.
> The transition from 32 to 64 bits brought the opportunity to 
> clean up the ISA. Because one thing that people often do not 
> know, is that ARM ISA has probably even more legacy baggage 
> than x86 (ARM encoding, thumbs, thumbs2, vfp, arm4, arm5, arm6, 
> arm7, etc.).
> It is often a problem and it happens in a lot of ISA's that 
> things that were good ideas for a certain process size become 
> real problems later on that slow down or block evolution. 
> Examples abound, double indirect addressing modes in m68k, 
> branch delay slots in MIPS and SPARC, register windows in 
> SPARC, memory based register in TMS9900, predicates, shifts and 
> PC in normal register in ARM, variable length encoding and 
> segments in x86 etc...




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