Fixing core.atomic

sarn sarn at theartofmachinery.com
Wed Jun 2 22:04:29 UTC 2021


On Wednesday, 2 June 2021 at 14:50:44 UTC, rm wrote:
> *snip*

Sorry, but I don't feel like anything you wrote relates to 
anything I actually said.  For example:

> Anyway, I disagree about the simple cases. Because specifically 
> the case of simple event counter that isn't require for 
> synchronization, you should be using relaxed. There is no need 
> for sequential consistency in this case.

The "simple cases" comment was about how the "thread-safe value" 
abstraction only works at all in a few simple cases (such as an 
event counter that doesn't affect flow of control).  No one has 
implied anything about what memory order you need for a counter.

But if you do consider memory order, that's more reason to treat 
atomic operations as explicit atomic *operations*, and not wrap 
them in a "thread-safe value" abstraction.


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