[dmd-concurrency] word tearing status in today's processors

[Robert Jacques]

On Wed, 27 Jan 2010 10:10:49 -0500, Andrei Alexandrescu  
<andrei at erdani.com> wrote:
> Hello,
>
>
> I'm looking _hard data_ on how today's processors address word tearing.  
> As usual, googling for word tearing yields the usual mix of vague  
> information, folklore, and opinionated newsgroup discussions.
>
> In particular:
>
> a) Can we assume that all or most of today's processors are able to  
> write memory at byte level?

 From an article on the Java Memory model:  
http://javaboutique.internet.com/articles/java_memory/
Word Tearing
Word Tearing occurs when some processors do not allow for a single byte to  
be updated individually. In old processors writes to memory are done  
through a word (two bytes), so in these cases the processor would read the  
whole word from memory and update the appropriate byte and then write the  
word back into memory. This is called word tearing. In modern processors  
this problem does not exist as they allow a single byte to be written to  
memory.

Summarized from a table: http://en.wikipedia.org/wiki/Word_(computing)
8 bit addressing resolution has been standard since the late 70s (with the  
exception of the cray)

 From Re: JavaMemoryModel: Word tearing  
(http://www.cs.umd.edu/~pugh/java/memoryModel/archive/0974.html) Circa 2002
  3) Word tearing is not an issue on most machines. SPARC (as of my V9  
manual)
specifies that loads and stores, even double-word, are atomic. PowerPC  
specifies
that all loads and stores up to the native word size are atomic. And while  
Intel
may not specify the semantics explicitly, mainstream manufacturers are  
unlikely to
go against the standard implementation.

 From an Intel forum:  
http://software.intel.com/en-us/forums/showthread.php?t=47453
"Recently I learned about word tearing in threaded programs and that it  
can occur on alpha processors."

"If a variable crosses the boundary between memory units, which can happen  
if the machine supports unaligned memory access, the computer may have to  
send the data in two bus transactions. An unaligned 32-bit value, for  
example, may be sent by writing the two adjacent 32-bit memory units. If  
either memory unit involved in the transaction is simultaneously written  
 from another processor, half of the value may be lost. This is called  
"word tearing.""

"Here are some extracts from the IA-32 Intel Architecture Software  
Developer's Manual Volume 3 : System Programming Guide
[start of quote]
7.1.1 Guaranteed Atomic Operations
The Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors  
guarantee that the following basic memory operations will always be  
carried out atomically:
. Reading or writing a byte
. Reading or writing a word aligned on a 16-bit boundary
. Reading or writing a doubleword aligned on a 32-bit boundary
The Pentium 4, Intel Xeon, and P6 family, and Pentium processors guarantee  
that the following additional memory operations will always be carried out  
atomically:
. Reading or writing a quadword aligned on a 64-bit boundary.
. 16-bit accesses to uncached memory locations that fit within a 32-bit  
data bus.
The P6 family processors guarantee that the following additional memory  
operations will always be carried out atomically:
. Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within  
a 32-byte cache line.
Accesses to cacheable memory that are split across bus widths, cache lines  
and page boundaries are not guaranteed to be atomic by the Pentium 4,  
Intel Xeon, P6 family, Pentium and Intel486 processors. The Pentium 4,  
Intel Xeon and P6 family processors provide bus control signals that  
permit external memory subsystems to make split accesses atomic; however,  
nonaligned data accesses will seriously impact the performance of the  
processor and should be avoided.
[end of quote]
"