ARM Cortex-M Broken Binaries with -O2 and -O3 (-fschedule-insns)

[Johannes Pfau via D.gnu]

Am Sat, 22 Jul 2017 08:11:28 +0000
schrieb Mike <none at none.com>:

> On Friday, 21 July 2017 at 23:44:53 UTC, Mike wrote:
> 
> > However, I'm getting broken binaries with -O2 and -O3.  I've 
> > nailed the culprit down to -fschedule-insns (i.e. if I add 
> > -fno-schedule-insns to -O2 or -O3, the binary works fine).  
> 
> I've confirmed that -fschedule-insns is reordering register 
> access even though they are being accessed with 
> volatileLoad/Store.  Read the comments in the following code for 
> understanding.  FYI A bit-banded address is a 32-bit address to a 
> single bit.
> 
> Here's the D code
> -----------------
> // This is a single atomic store to bit-banded address 0x42470048
> RCC.CR.HSEBYP.value = false;
> 
> // This is a single read-modify-write to non-bit-banded 32-bit 
> address 0x40023808
> with(RCC.CFGR)
> {
>      setValue
>      !(
>            MCO2,    0
>          , MCO2PRE, 0
>          , MCO1PRE, 0
>          , I2SSRC,  0
>          , MCO1,    0
>          , RTCPRE,  0
>          , HPRE,    0b000
>          , PPRE2,   0b100
>          , PPRE1,   0b101
>          , SW,      0
>      )();
> }
> 

I guess this doesn't happen for a reduced example directly using
volatileLoad/volatileStore? If you could provide such a reduced example
that'd be very useful.

-- Johannes