[Issue 16028] Incorrect cache size returned from core.cpuid

[via Digitalmars-d-bugs]

https://issues.dlang.org/show_bug.cgi?id=16028

Илья Ярошенко <ilyayaroshenko at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |ilyayaroshenko at gmail.com

--- Comment #1 from Илья Ярошенко <ilyayaroshenko at gmail.com> ---
This is compiles:

/++
Returns: cache size in KBs.
Params:
    cacheLevel = cache level (0 = L1d, 1 = L1i, 2 = L2 etc.)
+/
int getCacheSize(int cacheLevel)  
{
    enum functionID = 0x04;

    // Intel stores it's cache information in eax4, with ecx as index
    // The information received is as following:
    // ebx[31:22] = Ways of associativity
    // ebx[21:12] = Physical line partitions
    // ebx[11: 0] = Line size
    int[4] cpuInfo;
    asm
    {
        mov EAX, functionID;
        mov ECX, cacheLevel;
        cpuid;
        mov cpuInfo + 0x0, EAX;
        mov cpuInfo + 0x4, EBX;
        mov cpuInfo + 0x8, ECX;
        mov cpuInfo + 0xC, EDX;
    }
    int ways = cpuInfo[1] & 0xffc00000; // This receives bit 22 to 31 from the
ebx register
    ways >>= 22; // Bitshift it 22 bits to get the real value, since we started
reading from bit 22
    int partitions = cpuInfo[1] & 0x3ff800; // This receives bit 12 to 21
    partitions >>= 12; // Same here, bitshift 12 bits
    int lineSize = cpuInfo[1] & 0x7ff; // This receives bit 0 to 11
    int sets = cpuInfo[2]; // The sets are the value of the ecx register
    // All of these values needs one appended to them to get the real value
    int ret = (ways + 1) * (partitions + 1) * (lineSize + 1) * (sets + 1);
    assert(ret % 1024 == 0);
    return ret >> 10;
}

--