Transactional Memory: From Semantics to Silocon

[Sean Kelly]

Craig Black wrote:
> It seems an Intel research project is considering hardware support for 
> transactional memory.  I thought it would be interesting since 
> Transactional Memory will probably be included in D 2.0 at some point.
> 
> http://video.google.com/videoplay?docid=-5240896304418824367

I've been hoping some hardware manufacturer would add some level of 
transactional support.  I haven't watched the video yet, the the goal 
for me would be to simply allow transactions of a few memory accesses. 
Let's say enough to fill the L1 cache at most.  The goal would be to 
provide more flexibility than LL/SC, which is basically a transaction 
that is limited to one address.  I know there are algorithms which work 
around the single-address limitation for LL/SC and CAS, but they are far 
too clever for even most expert programmers to be expected to understand 
:-)  Hardware transactional memory would be much nicer.


Sean