Who Ordered Memory Fences on an x86?

[Nick Sabalausky]

"Russell Lewis" <webmaster at villagersonline.com> wrote in message 
news:geu020$6fd$1 at digitalmars.com...
> Nick Sabalausky wrote:
>> Call me a grumpy old fart, but I'd be happy just tossing fences in 
>> everywhere (when a multicore is detected) and be done with the whole 
>> mess, just because trying to wring every little bit of speed from, say, a 
>> 3+ GHz multicore processor strikes me as a highly unworthy pursuit. I'd 
>> rather optimize for the lower end and let the fancy overpriced crap 
>> handle it however it will.
>
> Ok, I'm not going to go as far as that.  :)  But I've heard that Intel has 
> been pondering doing almost that, at the hardware level.  The theory is 
> that years from now, our CPUs will not be "one or a few extremely complex 
> processors," but instead "hundreds or thousands of simplistic processors." 
> You could implement a pretty braindead execution model (no reordering, 
> etc.) if you had 1024 cores all working in parallel.
>
> The question, of course, is how fast the software will come along to the 
> point where it can actually make use of that many cores.

Yea, I've been hearing a lot about that. Be interesting to see what happens. 
Console gaming will probably be the best place to watch to see how that 
turns out (what with Sony's Cell and all).

Also, a few years ago I heard about some research on a "smart memory" chip 
that would allow certain basic operations to be performed within the memory 
chip itself (basically turning the memory cells into registers, AIUI). IIRC, 
the benefit they were aiming for was reducing the bottleneck of CPU<->RAM 
bus traffic. I haven't heard anything about it since then, but between that 
and the "lots of simple CPU cores" predictions, I wouldn't be surprised 
(though I'm not sure I would bet on it either) to eventually see traditional 
memory and processors (and maybe even hard drives) become replaced by a 
hybrid "CPU/RAM" chip.