Determing cache sizes -- request for testing

[Bruno Medeiros]

Don wrote:
> To implement efficient memory-intensive operations (memcpy, array 
> operations, matrix multiplication, etc), you really need to know the 
> sizes of the data caches.
> Although most modern CPUs provide methods to determine the sizes of 
> their built-in caches, it's a complete pigs breakfast. There are 
> multiple complicated methods, and documentation is scant.
> I've written some code to make this mess usable, and provide what you 
> really want. For each level of cache, the code provides size in KB, ways 
> of associativity, and the cache line size.
> 
> The attached code should eventually become part of std.cpuid, and an 
> equivalent module in Tango. But, it needs significant further testing.
> 
> Please compile and run the code, and report the results. Any results 
> would be useful, but particularly valuable would be:
> (1) Multicore AMD machines;
> (2) Early AMD machines (K6 or earlier).
> (3) Early Intel machines;
> (4) anything from another manufacturer.
> (5) any crashes or obvious bugs.
> 
> Public domain.
> 

Vendor string:    AuthenticAMD
Processor string: AMD Athlon(tm) 64 X2 Dual Core Processor 5000+
Signature:        Family=15 Model=107 Stepping=2
Features:         MMX FXSR SSE SSE2 SSE3 3DNow! 3DNow!+ MMX+ AMD64 HTT
Multithreading:   2 threads / 2 cores

Family=F Model=6B Stepping=2
Data caches:
Level 1 size=8K, ways=2 linesize=32
Level 2 size=512K, ways=16 linesize=64
Level 3 size=4194303K, ways=1 linesize=64

-- 
Bruno Medeiros - Software Developer, MSc. in CS/E graduate
http://www.prowiki.org/wiki4d/wiki.cgi?BrunoMedeiros#D