ARM bare-metal programming in D (cont) - volatile

[eles]

On Thursday, 24 October 2013 at 13:05:58 UTC, Iain Buclaw wrote:
> On 24 October 2013 12:22, eles <eles at eles.com> wrote:
>> On Thursday, 24 October 2013 at 08:20:43 UTC, Iain Buclaw 
>> wrote:
>>>
>>> On 24 October 2013 08:18, Mike <none at none.com> wrote:
>>>>
>>>> On Thursday, 24 October 2013 at 06:37:08 UTC, Iain Buclaw 
>>>> wrote:
>>>>>
>>>>>
>>>>> On 24 October 2013 06:37, Walter Bright 
>>>>> <newshound2 at digitalmars.com>
>>>>> wrote:
>>>>>>
>>>>>>
>>>>>> On 10/23/2013 5:43 PM, Mike wrote:

> The compiler does not cache shared data (at least in GDC).

Well, that should not be a matter of implementation, but of 
language standard.

Besides not caching, still MIA is the fact that these read/write 
operations should occur when asked, not later (orderly execution 
means almost nothing if all those operations are executed by the 
compiler at some time later, eventually not taking into account 
sleep()s between operations - sometimes the hardware needs, let's 
say, 500ms to guarantee a register is filled with a meaning value 
- and so on.

So it is about the correct memory location, the immediateness of 
those operations (this will also ensure orderly execution) and 
about the uncaching.