Intel MPX

[via Digitalmars-d]

On Tuesday, 16 December 2014 at 06:18:10 UTC, Leandro T. C. Melo 
via Digitalmars-d wrote:

> including special-purpose registers (4 of them), a bounds 
> directory/tables
> for storing/loading linearized pointer addresses, specific 
> instructions to
> independently make/check upper/lower bounds, and even modified 
> versions of
> call/ret/jump.

Yes, it is a very interesting move. It seems like Intel keeps 
focusing on adding features to cores rather than scaling up the 
number of cores. If this goes on, I think x86 will start to 
influence the design of languages and runtime capabilities.

Tying bounds to the address of the pointer seems to have 
implications for how one should structure programs too. I wonder 
how the avoid cache misses in the table lookup, though. I guess 
that is why they have modified instructions that modify the 
instruction pointer?

One of the interesting features of MPX is that you turn off MPX 
and then the CPU will treat MPX instructions as NOP instructions. 
So you can basically compile your server with MPX, and only turn 
it on when you run into trouble or when you have low load.

> ​They are working in the ABI level so calling conventions can 
> benefit from
> it. Although MPX currently supports only statically allocated 
> arrays, a
> memory-protected version of glibc is on the way​:
> https://software.intel.com/en-us/blogs/2013/07/22/intel-memory-protection-extensions-intel-mpx-support-in-the-gnu-toolchain

Yes, they are building MPX support into malloc, I believe. So 
anything malloc'ed will be bounds-checkable when you turn on full 
MPX instrumentation.

> ​I've tried out the MPX-enabled GCC version and it looks pretty 
> cool.

Did you run the MPX-enabled executable on an emulator?