H1 2015 Priorities and Bare-Metal Programming
Walter Bright via Digitalmars-d
digitalmars-d at puremagic.com
Sun Feb 1 13:52:13 PST 2015
On 2/1/2015 8:09 AM, Timo Sintonen wrote:
> I just pointed out that d had no way to access registers properly.
volatileLoad() and volatileStore() do the job correctly.
> DMD and GDC
> optimize very heavily and may cache, reorder and remove any access they think is
> not needed.
This is specifically not the case with compiler intrinsics volatileLoad() and
volatileStore().
> Other languages may not have such optimizations and registers can be accessed
> just with normal memory oprations.
The trouble with those is when memory mapped registers have specific behaviors
based on how and when read/write cycles occur. Many instructions are implicitly
read-modify-write, and may not offer sufficient control. volatileLoad() and
volatileStore() make the read/write operations and cycles explicit, even in the
presence of aggressive optimizations.
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