Very limited shared promotion

[Walter Bright]

On 6/22/2019 4:24 PM, Manu wrote:
> If you engage in @system code to distribute across threads, it's a no brainer to 
> expect that code to handle cache coherency measures. It would be broken if it 
> didn't.

It is not a no-brainer. Nowhere is it specified, and all the examples and 
tutorials I've seen say DO NOT follow an atomic write with a non-atomic read of 
the same variable in another thread. Not only that, it's usually a CENTRAL THEME 
of these expositions.

The only synchronization required (will be) for atomics, and that assumes atomic 
write followed by atomic read. Not atomic write followed by non-atomic read of 
the same memory.

The code may appear to work on the x86 because Intel CPUs do some additional 
not-required synchronization on reads. But it'll be leaving a nightmare for some 
poor sap who tries to port the code to the ARM.