x86 intrinsics for sale cheap

[Cecil Ward]

On Wednesday, 31 May 2023 at 16:07:55 UTC, Johan wrote:
> On Wednesday, 31 May 2023 at 15:58:53 UTC, Cecil Ward wrote:
>> On Wednesday, 31 May 2023 at 15:56:45 UTC, Cecil Ward wrote:
>>> I have been working on simple wrappers around new(ish) x86 
>>> instructions that are not otherwise accessible. Also with 
>>> replacement functions in straight D for machines where the 
>>> instruction is not available. Currently only for GDC as LDC 
>>> doesn’t support some of the features of GCC inline asm that I 
>>> am relying on  - named parameters in the asm with %[name] 
>>> syntax. But hopefully that will get fixed by the LDC 
>>> maintainers, so I will be able to work with either compiler. 
>>> My routines need more testing and a vast amount of cleanup. 
>>> So it’s early days.
>>>
>>> Is that something that you would be interested in for the D 
>>> runtime library? (For GDC / LDC ?) I unfortunately haven’t 
>>> attacked DMD yet because that uses a different inline asm 
>>> syntax, and would mean a rewrite. But that isn’t a problem 
>>> because thr DMD user gets the pure D replacement anyway due 
>>> to conditional compilation.
>>>
>>> If you are interested, then let me know. I do need help 
>>> testing though and some advice about unit tests.
>>
>> The instructions are those that were new with the Haswell 
>> micro architecture so that’s what ten years ago now, so now is 
>> the time that these instructions will become more usable for 
>> programmers worried about older machines, and there are the 
>> fallbacks too, as far as I have got with that.
>
> Are you aware of intel-intrinsics? 
> https://code.dlang.org/packages/intel-intrinsics
> It sounds like you are duplicating the effort; better to team 
> up with that project.
>
> -Johan

Yes, I am very aware, and was even thinking of using the same 
names. My goals are rather different though and I don’t use the 
same non-standard __xmm256 type names (or whatever). Those Intel 
routines don’t have a fallback equivalent though for machines 
where the instruction isn’t available so there’s some Intel sales 
promotion in there since you do need to have a sufficiently new 
CPU or nothing.

And I’m concentrating solely on D, not trying to write thing in 
C, put another wrapper round that for D and then hope it all 
still inlines with zero overhead parameter passing.

Lastly, those Intel intrinsics are I assume, unless I’m wrong, 
restricted to the Intel C/C++ compiler. And I’m GDC/LDC only.

So quite a gulf there and I’m not solely trying to do the same 
thing. And it’s D first, and with zero overhead being a 
requirement.