[dmd-concurrency] draft 7

[Fawzi Mohamed]

On 2-feb-10, at 01:34, Andrei Alexandrescu wrote:

> Fawzi Mohamed wrote:
>> you don't need a barrier, you need a volatile statement to avoid  
>> compiler optimizations
>
> That depends on the platform. On contemporary Intel machines I agree  
> there's no need for a barrier.

as I explained in another post (that I wrote several hours ago, but  
unfortunately was just sent (I closed the computer too fast...) I  
think that you don't really understand what barriers do.
Barriers introduce a partial ordering, they don't necessarily  
guarantee that the value in a local cache is immediately "synchronized".
The important thing (in the example of accessing a single value that  
is accessed atomically as in the example we are discussing about) is  
that it is really read from memory (even if through caches) and not  
from a register.
Noramally barriers are "global", but itanium began toying with more  
local barriers (that don't force the update of the whole cache), but  
even that does not change anything to the basic idea.
I am not aware of any hardware needing the kind of handshake you  
describe.
Even Alpha, that is the only processor that needs the extremely  
annoying dependent load barriers (I really hope that will never come  
back), does not need it.

Fawzi
>
> Andrei
>
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