[dmd-concurrency] shared arrays

[Andrei Alexandrescu]

Robert Jacques wrote:
>  From wikipedia:
> "Early AMD64 processors lacked the CMPXCHG16B instruction, which is an 
> extension of the CMPXCHG8B instruction present on most post-486 
> processors. Similar to CMPXCHG8B, CMPXCHG16B allows for atomic 
> operations on 128-bit double quadword (or oword) data types. This is 
> useful for parallel algorithms that use compare and swap on data larger 
> than the size of a pointer, common in lock-free and wait-free 
> algorithms. Without CMPXCHG16B one must use workarounds, such as a 
> critical section or alternative lock-free approaches"
> 
> So while 32-bit and 64-bit CPUs should have a 64-bit CAS, some 64-bit 
> CPUs won't have a 128-bit CAS. And since so many things (like arrays) go 
> from 64-bits to 128-bits when you switch from 32-bit DMD to 64-bit DMD, 
> I think assuming the presence of a double width CAS to be erroneous in 
> the language design.

Yah, I was asking whether we can assume long and double can be assumed 
atomically copyable. (But arrays won't.)

Andrei