[dmd-concurrency] word tearing status in today's processors

[Andrei Alexandrescu]

Hello,


I'm looking _hard data_ on how today's processors address word tearing. 
As usual, googling for word tearing yields the usual mix of vague 
information, folklore, and opinionated newsgroup discussions.

In particular:

a) Can we assume that all or most of today's processors are able to 
write memory at byte level?

b) If not, is it reasonable to have the compiler insert for sub-word 
shared assignments a call to a function that avoids word tearing by 
means of a CAS loop?

c) For 64-bit data (long and double), am I right in assuming that all 
non-ancient Intel32 processors do offer a means to atomically assign 
64-bit data? (What are those asm instructions?) For processors that 
don't (Intel or not), can we/should we guarantee at the language level 
that 64-bit writes are atomic? We could effect that by using e.g. a 
federation of hashed locks, or even (gasp!) two global locks, one for 
long and one for double, and do something cleverer when public outrage 
puts our lives in danger. Java guarantees atomic assignment for volatile 
data, but I'm not sure what mechanisms implementations use.


Thanks,

Andrei