[dmd-concurrency] word tearing status in today's processors

[Michel Fortin]

Le 2010-01-27 à 10:10, Andrei Alexandrescu a écrit :

> I'm looking _hard data_ on how today's processors address word tearing. As usual, googling for word tearing yields the usual mix of vague information, folklore, and opinionated newsgroup discussions.
> 
> In particular:
> 
> a) Can we assume that all or most of today's processors are able to write memory at byte level?

I'd like to have an answer to that. You're right that it's terribly difficult to get reliable information on this.

While I believe most have a write instruction at the byte level, I'm not sure if the memory coherency between processors can works at this granularity.

I think the best route would be to not make any assumption and offer an API where the user can detect atomic capabilities and seamlessly switch to the lock pool mechanism for variables where the needed atomic operations aren't available.

See my reply to Kevin.

-- 
Michel Fortin
michel.fortin at michelf.com
http://michelf.com/