[dmd-concurrency] word tearing status in today's processors

[Sean Kelly]

On Jan 27, 2010, at 10:00 AM, Andrei Alexandrescu wrote:

> Michel Fortin wrote:
>> Le 2010-01-27 à 10:10, Andrei Alexandrescu a écrit :
>>> I'm looking _hard data_ on how today's processors address word
>>> tearing. As usual, googling for word tearing yields the usual mix
>>> of vague information, folklore, and opinionated newsgroup
>>> discussions.
>>> In particular:
>>> a) Can we assume that all or most of today's processors are able to
>>> write memory at byte level?
>> I'd like to have an answer to that. You're right that it's terribly
>> difficult to get reliable information on this.
>> While I believe most have a write instruction at the byte level, I'm
>> not sure if the memory coherency between processors can works at this
>> granularity.
> 
> Well that only adds to the much folklore that I've pored through already :o). We sorely miss a hardcore low-level threads expert on this list.

I'm nearly certain this works on x86 because x86 can do atomic unaligned writes, which is basically the same as byte-level atomic writes.  I really couldn't say about other CPUs though.  I'd like to believe it's possible, but don't have data to back it up.  Might be worth looking at Joe Seigh's atomics library and seeing if it offers atomic ops at byte-level granularity.