RISC-V port

[Luís Marques]

I have druntime working with the RISC-V backend (32-bit / Newlib 
based; I got backend errors for 64-bit; I can't test glibc in 
32-bit because AFAIK there's no 32-bit RISC-V Linux).

It needed some workarounds due to the lack of proper atomics and 
TLS support in the backend, as well as Newlib limitations, but 
that's mostly taken care of. For Phobos to work properly the 
backend needs to support exceptions. Currently the backend seems 
to only emit code for the non-exceptional code path.

Does anyone here understand what an LLVM backend needs to do to 
get code generated for the exception stuff (e.g. landingpad, 
etc.)? I tried to look in the ARM backend but it wasn't very 
illuminating...