RISC-V port

Luís Marques luis at luismarques.eu
Thu May 17 15:38:42 UTC 2018

On Thursday, 17 May 2018 at 15:36:05 UTC, Luís Marques wrote:
> I have druntime working with the RISC-V backend (32-bit / 
> Newlib based; I got backend errors for 64-bit; I can't test 
> glibc in 32-bit because AFAIK there's no 32-bit RISC-V Linux).
> It needed some workarounds due to the lack of proper atomics 
> and TLS support in the backend, as well as Newlib limitations, 
> but that's mostly taken care of. For Phobos to work properly 
> the backend needs to support exceptions. Currently the backend 
> seems to only emit code for the non-exceptional code path.
> Does anyone here understand what an LLVM backend needs to do to 
> get code generated for the exception stuff (e.g. landingpad, 
> etc.)? I tried to look in the ARM backend but it wasn't very 
> illuminating...

To clarify: the LLVM IR generated by LDC has the whole code, but 
the backend behaves as if an exception could never be thrown, and 
the exception handling stuff gets optimized away. Or so it seems, 

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