Multicores and Publication Safety

[Sean Kelly]

Jb wrote:
> "Walter Bright" <newshound1 at digitalmars.com> wrote in message 
> news:g7855a$2sd3$1 at digitalmars.com...
>> "What memory fences are useful for on multiprocessors; and why you should 
>> care, even if you're not an assembly programmer."
>>
>> http://bartoszmilewski.wordpress.com/2008/08/04/multicores-and-publication-safety/
>>
>> http://www.reddit.com/comments/6uuqc/multicores_and_publication_safety/
> 
> None of that is relevant on x86 as far as I understand. I could only find 
> the one regarding x86-64, but as far as I know it's the same on x86-32.
> 
> http://www.intel.com/products/processor/manuals/318147.pdf
> 
> The key point being loads are not reordered with other loads, and stores are 
> not reordered with other stores.

Not true.  The actual behavior of IA-32 processors has been hotly 
debated, but it's been established that at least certain AMD processors 
may reorder loads.  Also, even under the PCsc model it is completely 
legal to "hoist" loads above stores, or equivalently, to "sink" stores 
below loads.  In short, unless you've *really* done your homework I 
suggest being very careful with respect to lock-free programming--ie. 
always perform fully sequenced operations just to be safe.  Tango has 
had such a module from the start, and it looks like Phobos2 may get one 
fairly soon as well.


Sean