On heap segregation, GC optimization and @nogc relaxing

[deadalnix via Digitalmars-d]

On Wednesday, 12 November 2014 at 08:38:14 UTC, Ola Fosheim 
Grøstad wrote:
> That changes over time. The current focus in upcoming hardware 
> is on:
>
> 1. Heterogenous architecture with high performance co-processors
>
> 2. Hardware support for transactional memory
>
> Intel CPUs might have buffered transactional memory within 5 
> years.
>

I'm sorry to be blunt, but there is nothing actionable in your 
comment. You are just throwing more and more into the pot until 
nobody know what there is in. But ultimately, the crux of the 
problem is the thing quoted above.

  1. No that do not change that much over time. The 
implementations details are changing, recent schemes become more 
complex to accommodate heterogeneous chips, but it is irrelevant 
here. What I've mentioned is true for all of them, and has been 
for at least 2 decades by now. There is no sign that this is 
gonna change.
  2. The transactional memory thing is completely orthogonal to 
the subject at hand so, as the details of implementation of 
modern chip, this doesn't belong here. In addition, the whole CPU 
industry is backpedaling on the transactional memory concept. 
That is awesome on the paper, but it didn't worked.

There is only 2 way to achieve good design. You remove useless 
things until there is obviously nothing wrong, or you add more 
and more until there is nothing obviously wrong. I won't follow 
you down the second road, so please stay on track.